1. Field of the Invention
This present invention relates to a non-volatile semiconductor memory, more particularly, a non-volatile semiconductor memory and a method for fabricating the same using Silicon On Insulator (SOI) technique.
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM) is known as a non-volatile semiconductor memory. In the EEPROM, a cell array is comprised in such a way that a memory cell transistor is arranged at an intersection where a word line in the row direction and a bit line in the column direction cross over each other. Among EEPROMs, the NAND flash EEPROM in which a plurality of memory cell transistors are connected in series, and which can erase all the written data simultaneously, has been in wide use.
A memory cell transistor of the NAND flash EEPROM includes n+-source and drain regions which are opposite to each other; and a p channel region between the source and drain regions. A stacked gate structure is formed on the channel region in which a control gate electrode and a floating gate electrode are stacked. Memory cell transistors adjacent to one another in the row direction are isolated from one another by an element isolation region. The NAND flash EEPROM experiences of fluctuations in gate threshold voltage due to influence of parasitic capacitance in the element isolation region between memory cell transistors and parasitic capacitance between an interconnect and a substrate, and the like.
In order to reduce the fluctuation in the gate threshold voltage due to the influence of the parasitic capacitance in the element isolation region and the parasitic capacitance between the interconnect and the substrate, a NAND flash EEPROM has been considered which employs SOI technology in which a semiconductor layer (SOI layer), arranged on the an embedded insulating layer (SOI insulator), serves as an active layer. According to the NAND flash EEPROM employing the SOI technology, the memory cell transistors adjacent to one another in the row direction are isolated from one another by the element isolation insulating film which is embedded as far as the SOI insulator, thereby enabling the parasitic capacitance in the element isolation region be reduced. In addition, since the SOI layer is formed on the SOI insulator, the parasitic capacitance between the interconnect and the substrate can be reduced, and hence the fluctuation in the gate threshold voltage can be reduced. As the memory cell transistor has been minaturized, an interval between the source and the drain of the memory cell transistor has become so narrower that influence of the short channel effect has increased in the NAND flash EEPROM employing the SOI technology.